Issued Patents All Time
Showing 26–35 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6925555 | System and method for determining a plurality of clock delay values using an optimization algorithm | Shen Lin, Osamu Nakagawa, Weize Xie | 2005-08-02 |
| 6661281 | Method for reducing current surge using multi-stage ramp shunting | Osamu Nakagawa, Shen Lin, Weize Xie, Xuejue Huang | 2003-12-09 |
| 6621305 | Partial swing low power CMOS logic circuits | Osamu Nakagawa, Shen Lin, Weize Xie, Kenynmyung Lee | 2003-09-16 |
| 6566924 | Parallel push algorithm detecting constraints to minimize clock skew | Shen Lin, Keunmyung Lee, Osamu Nakagawa, Weize Xie | 2003-05-20 |
| 6567960 | System for improving circuit simulations by utilizing a simplified circuit model based on effective capacitance and inductance values | Yu Cao, Osamu Nakagawa, Shen Lin, Weize Xie | 2003-05-20 |
| 6434724 | Method for extracting inductance parameters from a circuit design | Shen Lin, O. Samual Nakagawa | 2002-08-13 |
| 6412101 | Simultaneous path optimization (SPO) system and method | John D Wanek | 2002-06-25 |
| 6018623 | Method and system for determining statistically based worst-case on-chip interconnect delay and crosstalk | Valery Kanevsky, O. Sam Nakagawa, Soo Young Oh | 2000-01-25 |
| 5946482 | Method and apparatus for using parameters to simulate an electronic circuit | Lee A. Barford, Boris Troyanovsky | 1999-08-31 |
| 5610833 | Computer-aided design methods and apparatus for multilevel interconnect technologies | Keh-Jeng Chang, Keunmyung Lee, Soo Young Oh | 1997-03-11 |