AB

Ajay Singh Bisht

AN Ansys: 5 patents #15 of 298Top 6%
SY Synopsys: 3 patents #460 of 2,302Top 20%
CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
📍 San Jose, CA: #6,939 of 32,062 inventorsTop 25%
🗺 California: #66,801 of 386,348 inventorsTop 20%
Overall (All Time): #548,450 of 4,157,543Top 15%
9
Patents All Time

Issued Patents All Time

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDate
12106157 Memory efficient and scalable approach to stimulus (waveform) reading Anup Kumar Sultania, Mark W. Brown 2024-10-01
11734080 Memory efficient and scalable approach to stimulus (waveform) reading Anup Kumar Sultania, Mark W. Brown 2023-08-22
11630934 Integrated circuit analysis using a multi-level data hierarchy implemented on a distributed compute and data infrastructure Jayanta Roy, Mark W. Brown, Arney Deshpande, Yibing Wang, Ramakrishnan Balasubramanian 2023-04-18
10628543 Systems and methods for estimating a power consumption of a register-transfer level circuit design Renuka Vanukuri, Allen Baker 2020-04-21
10417365 Systems and methods for reducing power consumption of latch-based circuits Allen Baker 2019-09-17
10248746 Method and apparatus for estimating ideal power of an integrated circuit design Jayanta Roy, Kamlesh Kumar Madheshiya, Kunwar Prashant 2019-04-02
10133839 Systems and methods for estimating a power consumption of a register-transfer level circuit design Renuka Vanukuri, Allen Baker 2018-11-20
10083267 Systems and methods for reducing power consumption of latch-based circuits Allen Baker 2018-09-25
9892227 Systems, methods and storage media for clock tree power estimation at register transfer level 2018-02-13