Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8108653 | Processor architectures for enhanced computational capability and low latency | Boris Lerner | 2012-01-31 |
| 8078834 | Processor architectures for enhanced computational capability | — | 2011-12-13 |
| RE40904 | Apparatus for generating target addresses within a circular buffer including a register for storing position and size of the circular buffer | — | 2009-09-01 |
| 6513125 | Multi-phase multi-access pipeline memory system in which the pipeline memory can decode addresses issued by one processor while simultaneously accessing memory array by other processor | — | 2003-01-28 |
| 6510510 | Digital signal processor having distributed register file | — | 2003-01-21 |
| 6332188 | Digital signal processor with bit FIFO | Alexei Zatsman, Aryeh Lezerovitz, Zvi Greenfield, David R. Levine, Jose Fridman | 2001-12-18 |
| 6061779 | Digital signal processor having data alignment buffer for performing unaligned data accesses | — | 2000-05-09 |
| 6002882 | Bidirectional communication port for digital signal processor | — | 1999-12-14 |
| 5954811 | Digital signal processor architecture | — | 1999-09-21 |
| 5922076 | Clocking scheme for digital signal processor system | — | 1999-07-13 |
| 5896543 | Digital signal processor architecture | — | 1999-04-20 |
| 5787488 | Multi-phase multi-access pipeline memory system | — | 1998-07-28 |
| 5685005 | Digital signal processor configured for multiprocessing | Ronnin Yee, Mark A. Valley, Steven L. Cox | 1997-11-04 |
| 5634076 | DMA controller responsive to transition of a request signal between first state and second state and maintaining of second state for controlling data transfer | Mark A. Valley | 1997-05-27 |
| 5623621 | Apparatus for generating target addresses within a circular buffer including a register for storing position and size of the circular buffer | — | 1997-04-22 |
| 5619720 | Digital signal processor having link ports for point-to-point communication | Aaron Gorius | 1997-04-08 |
| 5611075 | Bus architecture for digital signal processor allowing time multiplexed access to memory banks | — | 1997-03-11 |
| 5471607 | Multi-phase multi-access pipeline memory system | — | 1995-11-28 |
| 5396608 | Method and apparatus for accessing variable length words in a memory array | — | 1995-03-07 |
| 5111431 | Register forwarding multi-port register file | — | 1992-05-05 |
| 4811296 | Multi-port register file with flow-through of data | — | 1989-03-07 |
| 4791551 | Microprogrammable devices using transparent latch | — | 1988-12-13 |
| 4769564 | Sense amplifier | — | 1988-09-06 |