IP

Indrani Paul

AM AMD: 54 patents #120 of 9,279Top 2%
DP Dell Products: 9 patents #739 of 6,820Top 15%
🗺 Texas: #1,525 of 125,132 inventorsTop 2%
Overall (All Time): #48,338 of 4,157,543Top 2%
53
Patents All Time

Issued Patents All Time

Showing 26–50 of 53 patents

Patent #TitleCo-InventorsDate
10649514 Method and apparatus for temperature and voltage management control Wei Huang, Yazhou Zu 2020-05-12
10613957 Achieving balanced execution through runtime detection of performance variation Brian J. Kocoloski, Leonardo Piga, Wei Huang 2020-04-07
10355966 Managing variations among nodes in parallel system frameworks Samuel Lawrence Wasmundt, Leonardo Piga, Wei Huang, Manish Arora 2019-07-16
10168762 Power management for heterogeneous computing systems Can Hankendi, Manish Arora 2019-01-01
10133574 Power management of instruction processors in a system-on-a-chip Akanksha Jain, Wei Huang 2018-11-20
10048741 Bandwidth-aware multi-frequency performance estimation mechanism Md Abdullah Shahneous Bari, Leonardo Piga 2018-08-14
10025361 Power management across heterogeneous processing units Vignesh Trichy Ravi, Manish Arora, Srilatha Manne 2018-07-17
9990203 Hardware accuracy counters for application precision and quality feedback Leonardo de Paula Rosa Piga, Abhinandan Majumdar, Wei-Ming Huang, Manish Arora, Joseph L. Greathouse 2018-06-05
9983652 Balancing computation and communication power in power constrained clusters Leonardo Piga, Wei Huang 2018-05-29
9965343 System and method for determining concurrency factors for dispatch size of parallel processor kernels Rathijit Sen, Wei Huang 2018-05-08
9947386 Thermal aware data placement and compute dispatch in a memory system Manish Arora, Yasuko Eckert, Nuwan Jayasena, Dong Zhang 2018-04-17
9946319 Setting power-state limits based on performance coupling and thermal coupling between entities in a computing device Manish Arora, Srilatha Manne, William L. Bircher 2018-04-17
9886326 Thermally-aware process scheduling Manish Arora, William L. Bircher 2018-02-06
9851777 Power gating based on cache dirtiness Manish Arora, Yasuko Eckert, Nuwan Jayasena, Srilatha Manne, Madhu Saravana Sibi Govindan +1 more 2017-12-26
9658663 Thermally-aware throttling in a three-dimensional processor stack Wei Huang, Manish Arora, Yasuko Eckert 2017-05-23
9619290 Hardware and runtime coordinated load balancing for parallel applications Peter Bailey, Manish Arora 2017-04-11
9507410 Decoupled selective implementation of entry and exit prediction for power gating processor components Yasuko Eckert, Manish Arora 2016-11-29
9443561 Ring networks for intra- and inter-memory I/O including 3D-stacked memories David A. Roberts, Yasuko Eckert, Mitesh R. Meswani 2016-09-13
9261938 Controlling energy consumption of an electronic device in response to availability of an energy source Manish Arora, Vignesh Trichy Ravi 2016-02-16
9164862 System and method for dynamically detecting storage drive type John Loffink 2015-10-20
9146580 System and method for multiple backplane time synchronization Timothy M. Lambert 2015-09-29
8738817 System and method for mapping a logical drive status to a physical drive status for multiple storage drives having different storage technologies within a server Timothy M. Lambert 2014-05-27
8656223 Peripheral component interconnect express root port mirroring Johan Rahardjo, Mukund P. Khatri 2014-02-18
8583847 System and method for dynamically detecting storage drive type John Loffink, Timothy M. Lambert 2013-11-12
8527803 System and method for multiple backplane time synchronization Timothy M. Lambert 2013-09-03