Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7770049 | Controller for clock skew determination and reduction based on a lead count over multiple clock cycles | Shawn Searles, Scott C. Johnson, Ravinder Reddy Rachala | 2010-08-03 |
| 7765425 | Incrementally adjustable skew and duty cycle correction for clock signals within a clock distribution network | Shawn Searles, Ravinder Reddy Rachala, Scott C. Johnson | 2010-07-27 |
| 6584594 | Data pre-reading and error correction circuit for a memory device | — | 2003-06-24 |
| 6438726 | Method of dual use of non-volatile memory for error correction | — | 2002-08-20 |
| 6360347 | Error correction method for a memory device | — | 2002-03-19 |
| 5257360 | Re-configurable block length cache | Paul G. Schnizlein | 1993-10-26 |
| 5153455 | "Transition-based wired ""OR"" for VLSI systems" | — | 1992-10-06 |
| 5041738 | CMOS clock generator having an adjustable overlap voltage | — | 1991-08-20 |
| 4841279 | CMOS RAM data compare circuit | — | 1989-06-20 |
| 4825101 | Full-level, fast CMOS output buffer | — | 1989-04-25 |
| 4806794 | Fast, low-noise CMOS output buffer | — | 1989-02-21 |
| 4804871 | Bit-line isolated, CMOS sense amplifier | — | 1989-02-14 |
| 4800300 | High-performance, CMOS latch for improved reliability | — | 1989-01-24 |
| 4761567 | Clock scheme for VLSI systems | Gigy Baror | 1988-08-02 |