| 10509740 |
Mutual exclusion in a non-coherent memory hierarchy |
— |
2019-12-17 |
| 10152436 |
Mutual exclusion in a non-coherent memory hierarchy |
— |
2018-12-11 |
| 9678872 |
Memory paging for processors using physical addresses |
— |
2017-06-13 |
| 8478944 |
Method and apparatus for adaptive cache frame locking and unlocking |
Harry Dwyer |
2013-07-02 |
| 8261022 |
Method and apparatus for adaptive cache frame locking and unlocking |
Harry Dwyer |
2012-09-04 |
| 8191067 |
Method and apparatus for establishing a bound on the effect of task interference in a cache memory |
Michael R. Betker, Harry Dwyer |
2012-05-29 |
| 7577791 |
Virtualized load buffers |
Ramesh Peri, Ravi Kolagotia |
2009-08-18 |
| 7533232 |
Accessing data from different memory locations in the same cycle |
Ramesh Peri, Ravi Kolagotla, Srinivas Doddapaneni |
2009-05-12 |
| 7383455 |
Method and apparatus for transferring multi-source/multi-sink control signals using a differential signaling technique |
Hyun Lee, Trevor Edward Little |
2008-06-03 |
| 7353513 |
Method and apparatus for establishing a bound on the effect of task interference in a cache memory |
Michael R. Betker, Harry Dwyer |
2008-04-01 |
| 7346735 |
Virtualized load buffers |
Ramesh Peri, Ravi Kolagotla |
2008-03-18 |
| 6874057 |
Method and apparatus for cache space allocation |
Harry Dwyer |
2005-03-29 |
| 6874056 |
Method and apparatus for reducing cache thrashing |
Harry Dwyer |
2005-03-29 |
| 6754748 |
Method and apparatus for distributing multi-source/multi-sink control signals among nodes on a chip |
Hyun Lee, Trevor Edward Little |
2004-06-22 |
| 6434163 |
Transverse correlator structure for a rake receiver |
Mohit Kishore Prasad |
2002-08-13 |
| 6397240 |
Programmable accelerator for a programmable processor system |
Stefan Thurnhofer |
2002-05-28 |
| 6272616 |
Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths |
Stefan Thurnhofer |
2001-08-07 |
| 6269440 |
Accelerating vector processing using plural sequencers to process multiple loop iterations simultaneously |
Frank T. Lemmon, Shaun P. Whalen |
2001-07-31 |
| 6052766 |
Pointer register indirectly addressing a second register in the processor core of a digital processor |
Michael R. Betker, Frank T. Lemmon, Shaun P. Whalen |
2000-04-18 |
| 5805489 |
Digital microprocessor device having variable-delay division hardware |
— |
1998-09-08 |
| 5802360 |
Digital microprocessor device having dnamically selectable instruction execution intervals |
— |
1998-09-01 |
| 5761492 |
Method and apparatus for uniform and efficient handling of multiple precise events in a processor by including event commands in the instruction set |
Shaun P. Whalen |
1998-06-02 |
| 5025365 |
Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors |
Sanjay Mathur |
1991-06-18 |