Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6730601 | Methods for fabricating a metal-oxide-metal capacitor | Yifeng Winston Yan, Sailesh Mansinh Merchant | 2004-05-04 |
| 6656850 | Method for in-situ removal of side walls in MOM capacitor formation | Simon John Molloy, Nace Layadi, Sidhartha Sen | 2003-12-02 |
| 6576563 | Method of manufacturing a semiconductor device employing a fluorine-based etch substantially free of hydrogen | Stephen W. Downey, Paul B. Murphey | 2003-06-10 |
| 6570238 | Preweakened on chip metal fuse using dielectric trenches for barrier layer isolation | Frank Hui | 2003-05-27 |
| 6525358 | Capacitor having the lower electrode for preventing undesired defects at the surface of the metal plug | Sailesh Mansinh Merchant, Yifeng Winston Yan | 2003-02-25 |
| 6498364 | Capacitor for integration with copper damascene processes | Stephen W. Downey, Sailesh Mansinh Merchant | 2002-12-24 |
| 6458648 | Method for in-situ removal of side walls in MOM capacitor formation | Simon John Molloy, Nace Layadi, Sidhartha Sen | 2002-10-01 |
| 6373087 | Methods of fabricating a metal-oxide-metal capacitor and associated apparatuses | Yifeng Winston Yan, Sailesh Mansinh Merchant | 2002-04-16 |
| 6323044 | Method of forming capacitor having the lower metal electrode for preventing undesired defects at the surface of the metal plug | Sailesh Mansinh Merchant, Yifeng Winston Yan | 2001-11-27 |
| 6323111 | Preweakened on chip metal fuse using dielectric trenches for barrier layer isolation | Frank Hui | 2001-11-27 |
| 6287952 | Method of etching self-aligned vias to metal using a silicon nitride spacer | — | 2001-09-11 |