Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7248079 | Differential buffer circuit with reduced output common mode variation | Makeshwar Kothandaraman, John C. Kriz, Bernard L. Morris | 2007-07-24 |
| 7218169 | Reference compensation circuit | Makeshwar Kothandaraman, John C. Kriz, Bernard L. Morris, Jeffrey J. Nagy, Stefan A. Siegel | 2007-05-15 |
| 7196561 | Programmable reset signal that is independent of supply voltage ramp rate | John C. Kriz, Duane J. Loeper, Antonio M. Marques | 2007-03-27 |
| 7177978 | Generating and merging lookup results to apply multiple features | Bhushan Mangesh Kanekar, Venkateshwar Rao Pullela, Dileep K. Devireddy, Gyaneshwar S. Saharia, Qizhong Chen | 2007-02-13 |
| 7145364 | Self-bypassing voltage level translator circuit | Makeshwar Kothandaraman, John C. Kriz, Bernard L. Morris, Yehuda Smooha | 2006-12-05 |
| 7139928 | Method and system for providing redundancy within a network element | Michael R. Smith, Kevin D. Morishige | 2006-11-21 |
| 7106107 | Reliability comparator with hysteresis | John C. Kriz, Bernard L. Morris, William B. Wilson | 2006-09-12 |
| 7098694 | Overvoltage tolerant input buffer | John C. Kriz, Bernard L. Morris | 2006-08-29 |
| 7068074 | Voltage level translator circuit | Makeshwar Kothandaraman, John C. Kriz, Antonio M. Marques, Bernard L. Morris | 2006-06-27 |
| 7057545 | Semiconductor resistance compensation with enhanced efficiency | Makeshwar Kothandaraman, John C. Kriz, Bernard L. Morris | 2006-06-06 |
| 7047385 | High-speed memory for use in networking systems | Jeff Hirschman | 2006-05-16 |
| 7034653 | Semiconductor resistor | John C. Kriz, Stefan A. Siegel, Joseph E. Simko, Yehuda Smooha | 2006-04-25 |
| 6992489 | Multiple voltage level detection circuit | John C. Kriz, Joseph E. Simko | 2006-01-31 |
| 6826150 | Distriburted QoS policing system and method | Yiren Ronnie Huang, Raymond Kloth, Ketan A. Padwekar | 2004-11-30 |
| 6774698 | Voltage translator circuit for a mixed voltage circuit | Makeshwar Kothandaraman, John C. Kriz, Bernard L. Morris, Stefan A. Siegel | 2004-08-10 |
| 5918072 | System for controlling variable length PCI burst data using a dummy final data phase and adjusting the burst length during transaction | — | 1999-06-29 |
| 5805905 | Method and apparatus for arbitrating requests at two or more levels of priority using a single request line | Sukalpa Biswas, Mark Williams | 1998-09-08 |
| 5577214 | Programmable hold delay | — | 1996-11-19 |
| 5469555 | Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system | Subir Ghosh | 1995-11-21 |
| 5463759 | Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system | Subir Ghosh | 1995-10-31 |
| 5448742 | Method and apparatus for local memory and system bus refreshing with single-port memory controller and rotating arbitration priority | — | 1995-09-05 |
| 5371880 | Bus synchronization apparatus and method | — | 1994-12-06 |