Issued Patents 2025
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431412 | Contact plugs for semiconductor device and method of forming same | Yasutoshi Okuno, Sung-Li Wang, Pang-Yen Tsai, Shen-Nan Lee, Teng-Chun Tsai | 2025-09-30 |
| 12426291 | Contact and via structures for semiconductor devices | Keng-Chu Lin | 2025-09-23 |
| 12389674 | Low resistance fill metal layer material as stressor in metal gates | Ziwei Fang, Keng-Chu Lin, Hsueh Wen Tsau | 2025-08-12 |
| 12362281 | Partial barrier free vias for cobalt-based interconnects and methods of fabrication thereof | Tsung-Ling Tsai, Shen-Nan Lee, Chung-Wei Hsu, Chen-Hao Wu, Teng-Chun Tsai | 2025-07-15 |
| 12347725 | Semiconductor structure with material modification and low resistance plug | Akira Mineji | 2025-07-01 |
| 12341013 | Method and structure for barrier-less plug | Sung-Li Wang, Hung-Yi Huang, Yu-Yun Peng, Chia-Hung Chu, Shuen-Shin Liang +1 more | 2025-06-24 |
| 12328938 | Gate structures for stacked semiconductor devices | Sathaiya Mahaveer DHANYAKUMAR, Huicheng Chang, Keng-Chu Lin | 2025-06-10 |
| 12315863 | Contact structures in semiconductor devices | Wei-Yen Woon, Cheng-Ming Lin, Han-Yu Lin, Szu-Hua Chen | 2025-05-27 |
| 12266688 | Semiconductor device with source/drain contact formed using bottom-up deposition | Sung-Li Wang, Yasutoshi Okuno | 2025-04-01 |
| 12266709 | Selective dual silicide formation using a maskless fabrication process flow | Pang-Yen Tsai, Yasutoshi Okuno | 2025-04-01 |
| 12255239 | Liner layer for backside contacts of semiconductor devices | Keng-Chu Lin, Yu-Yun Peng | 2025-03-18 |
| 12255249 | Inner spacer structures for gate-all-around field effect transistors | Keng-Chu Lin, Yu-Yun Peng | 2025-03-18 |
| 12243915 | Graphene wrap-around contact | Wei-Yen Woon | 2025-03-04 |