Issued Patents 2025
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424444 | Soft ashing process for forming protective layer on conductive cap layer of semiconductor device | Guan-Xuan Chen, Sheng-Liang Pan, Chia-Yang Hung, Po-Chuan Wang | 2025-09-23 |
| 12389667 | Fin field-effect transistor device and method | Meng Jhe Tsai, Hong-Jie Yang, Meng-Chun Chang, Hao Chiang, Chia-Ying Lee +1 more | 2025-08-12 |
| 12349435 | Vertical device having a protrusion source | De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee +1 more | 2025-07-01 |
| 12293947 | Gap patterning for metal-to-source/drain plugs in a semiconductor device | Yu-Lien Huang, Ching-Feng Fu, Fu-Sheng Li, Tsai-Jung Ho, Bor Chiuan Hsieh +2 more | 2025-05-06 |
| 12293910 | Interconnect structure for semiconductor devices | Po-Chuan Wang, Guan-Xuan Chen, Chia-Yang Hung, Sheng-Liang Pan | 2025-05-06 |
| 12278277 | Fin field-effect transistor and method of forming the same | Sheng-Liang Pan, Yung Tzu Chen, Chung-Chieh Lee, Yung-Chang Hsu, Chia-Yang Hung +2 more | 2025-04-15 |
| 12272731 | Middle-of-line interconnect structure and manufacturing method | Yu-Lien Huang, Ching-Feng Fu | 2025-04-08 |
| 12268027 | Middle-of-line interconnect structure and manufacturing method | Yu-Lien Huang, Ching-Feng Fu | 2025-04-01 |
| 12237228 | Semiconductor device and method | Shao-Jyun Wu, Hung-Chi Wu, Chia-Ching Lee, Pin-Hsuan Yeh, Hung-Chin Chung +3 more | 2025-02-25 |
| 12219882 | Memory cell with low resistance top electrode contact and methods for forming the same | Hsing-Hsiang WANG, Yu-Feng Yin, Jiann-Horng Lin | 2025-02-04 |
| 12205816 | Interconnect structure for semiconductor devices | Po-Chuan Wang, Guan-Xuan Chen, Chia-Yang Hung, Sheng-Liang Pan | 2025-01-21 |