Issued Patents 2025
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12432990 | Epitaxial source/drain feature with enlarged lower section interfacing with backside via | Wei-Yang Lee, Chia-Pin Lin | 2025-09-30 |
| 12408347 | Method for forming a 3-D semiconductor memory structure comprising horizontal and vertical conductive lines | Chih Hsuan Cheng, Chieh-Fang Chen, Sheng-Chen Wang, Chieh-Yi Shen, Han-Jong Chia +4 more | 2025-09-02 |
| 12408363 | Semiconductor device with phosphorus-doped epitaxial features | Chung-Chi Wen, Wei-Yuan Lu, Feng-Cheng Yang, Yen-Ming Chen | 2025-09-02 |
| 12408377 | Semiconductor device structure with backside contact | Wei-Yang Lee, Chia-Pin Lin | 2025-09-02 |
| 12369383 | Semiconductor structure with gate-all-around devices and stacked FinFET devices | Wei-Yang Lee, Chia-Pin Lin | 2025-07-22 |
| 12356662 | Asymmetric source/drain for backside source contact | Wei-Yang Lee, Chia-Pin Lin | 2025-07-08 |
| 12324201 | Integrated circuit device with source/drain barrier | Wei-Yang Lee, Yen-Ming Chen, Feng-Cheng Yang | 2025-06-03 |
| 12279451 | Semiconductor device including source/drain feature with multiple epitaxial layers | Chung-Chi Wen, Chia-Pin Lin | 2025-04-15 |
| 12272729 | Asymmetric source/drain for backside source contact | Wei-Yang Lee, Chia-Pin Lin | 2025-04-08 |
| 12245432 | Memory device and manufacturing method thereof | Feng-Cheng Yang, Katherine H. Chiang, Chung-Te Lin, Chieh-Fang Chen | 2025-03-04 |
| 12211749 | Cut EPI process and structures | Wei-Yang Lee, Chia-Pin Lin | 2025-01-28 |