Issued Patents 2025
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393505 | Reset circuitry providing independent reset signal for trace and debug logic | Amritanshu Anand, Satinder Singh Malhi | 2025-08-19 |
| 12298872 | Glitch suppression apparatus and method | — | 2025-05-13 |
| 12272416 | ATPG testing method for latch based memories, for area reduction | Venkata Narayanan Srinivasan, Balwinder Singh Soni | 2025-04-08 |
| 12210609 | Central controller for multiple development ports | Thomas Szurmant | 2025-01-28 |