Issued Patents 2025
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12432898 | Memory device having tiers of 2-transistor memory cells | Durai Vishak Nirmal Ramaswamy, Haitao Liu, Karthik Sarpatwari | 2025-09-30 |
| 12408388 | Ferroelectric transistors and assemblies comprising ferroelectric transistors | Haitao Liu, Durai Vishak Nirmal Ramaswamy | 2025-09-02 |
| 12361977 | Memory device having shared read/write data line for 2-transistor vertical memory cell | Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy | 2025-07-15 |
| 12349335 | Memory device having 2-transistor vertical memory cell and shared channel region | Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy, Haitao Liu | 2025-07-01 |
| 12336288 | Array of vertical transistors and method used in forming an array of vertical transistors | Yi Fang Lee, Jaydip Guha, Lars Heineck, Si-Woo Lee, Terrence B. McDaniel +3 more | 2025-06-17 |
| 12284805 | String driver assemblies including two-dimensional materials, and related memory devices | Akira Goda, Sanh D. Tang, Gurtej S. Sandhu, Litao Yang, Haitao Liu | 2025-04-22 |
| 12283636 | Devices including channel materials and passivation materials | Haitao Liu | 2025-04-22 |
| 12279434 | NAND structures with polarized materials | Albert Fayrushin, Gianpietro Carnevale, Aurelio Giancarlo Mauri | 2025-04-15 |
| 12266660 | Memory device having 2-transistor memory cell and access line plate | Karthik Sarpatwari, Haitao Liu, Durai Vishak Nirmal Ramaswamy | 2025-04-01 |
| 12256541 | Apparatus and method including memory device having 2-transistor vertical memory cell | Durai Vishak Nirmal Ramaswamy | 2025-03-18 |
| 12218236 | Devices including heterogeneous channels, and related memory devices, electronic systems, and methods | Scott E. Sills, Ramanathan Gandhi, Durai Vishak Nirmal Ramaswamy, Yi Fang Lee | 2025-02-04 |
| 12219750 | Memory device having 2-transistor vertical memory cell and separate read and write gates | Eric Carman, Durai Vishak Nirmal Ramaswamy, Richard E. Fackenthal, Karthik Sarpatwari, Haitao Liu +2 more | 2025-02-04 |
| 12219758 | Integrated assemblies having transistor body regions coupled to carrier-sink-structures; and methods of forming integrated assemblies | Haitao Liu, Durai Vishak Nirmal Ramaswamy, Yunfei Gao, Sanh D. Tang, Deepak Chandra Pandey | 2025-02-04 |
| 12219783 | Semiconductor devices and hybrid transistors | Haitao Liu, Durai Vishak Nirmal Ramaswamy | 2025-02-04 |
| 12213321 | Memory device having 2-transistor vertical memory cell and conductive shield structure | Richard E. Fackenthal, Durai Vishak Nirmal Ramaswamy | 2025-01-28 |
| 12200928 | Memory device having memory cell strings and separate read and write control gates | Haitao Liu, Albert Fayrushin, Yingda Dong | 2025-01-14 |
| 12200938 | Driver placement in memories having stacked memory arrays | Haitao Liu, Gurtej S. Sandhu, Sanh D. Tang, Akira Goda, Lifang Xu | 2025-01-14 |
| 12191354 | Vertical transistors having at least 50% grain boundaries offset between top and bottom source/drain regions and the channel region that is vertically therebetween | Manuj Nahar, Vassil Antonov, Michael Mutch, Hung-Wei Liu, Jeffery B. Hull | 2025-01-07 |