Issued Patents 2025
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411657 | Asynchronous full-adder with majority or minority gates to generate carry-out true output | Amrita Mathuriya, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2025-09-09 |
| 12405768 | Asynchronous full-adder with majority or minority gates to generate carry-out false output | Amrita Mathuriya, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2025-09-02 |
| 12379898 | Asynchronous full-adder with majority or minority gates to generate sum false output | Amrita Mathuriya, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2025-08-05 |