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Device, method, and system to facilitate improved bandwidth of a branch prediction unit |
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De-prioritizing speculative code lines in on-chip caches |
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Method and apparatus for leveraging simultaneous multithreading for bulk compute operations |
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Techniques for accelerating neural networks |
Gurpreet Singh Kalsi, Ramachandra Chakenalli Nanjegowda, Kamlesh Pillai |
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Throttling code fetch for speculative code paths |
Anant Vithal Nori, Prathmesh Kallurkar, Niranjan Soundararajan |
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Techniques to repurpose static random access memory rows to store a look-up-table for processor-in-memory operations |
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Methods and apparatus to profile page tables for memory management |
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System, method, and apparatus for enhanced pointer identification and prefetching |
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Segmented branch target buffer based on branch instruction type |
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Methods, apparatus, and articles of manufacture to reorder N-dimensional sparse data into groups of data elements that can be collocated in a memory |
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