Issued Patents 2025
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12394492 | Memory cell sensing circuit with adjusted bias from pre-boost operation | Bayan Nasri, Tzu-Ning Fang, Rezaul Haque, Dhanashree Kulkarni, Narayanan Ramanan +4 more | 2025-08-19 |
| 12394497 | Efficient bitline stabilization for program inhibit in NAND arrays | Tarek Ahmed Ameen Beshari, Ahsanur Rahman, Sagar Upadhyay, Pratyush Chandrapati | 2025-08-19 |
| 12334152 | Simultaneous programming of multiple sub-blocks in NAND memory structures | Ali Khakifirooz, Pranav Kalavade, Tarek Ahmed Ameen Beshari | 2025-06-17 |
| 12322455 | Program verify process having placement aware pre-program verify (PPV) bucket size modulation | Tarek Ahmed Ameen Beshari, Matin Amani, Narayanan Ramanan, Arun Thathachary | 2025-06-03 |
| 12243590 | Method and apparatus for improving write uniformity in a memory device | Christian Mion, Pranav Kalavade, Rohit S. Shenoy, Xin Sun, Kristopher H. Gaewsky | 2025-03-04 |
| 12237023 | Dynamic detection and dynamic adjustment of sub-threshold swing in a memory cell sensing circuit | Tarek Ahmed Ameen Beshari, Matin Amani, Narayanan Ramanan | 2025-02-25 |
| 12224019 | Cache processes with adaptive dynamic start voltage calculation for memory devices | Xiang Yang, Ali Khakifirooz, Pranav Kalavade | 2025-02-11 |
| 12211563 | Dynamic gate steps for last-level programming to improve write performance | Sagar Upadhyay, Archana Tankasala, Aliasgar S. Madraswala | 2025-01-28 |
| 12189955 | Skip program verify for dynamic start voltage sampling | Archana Tankasala, Sagar Upadhyay, Aliasgar S. Madraswala | 2025-01-07 |