Issued Patents 2025
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417792 | Jitter reduction in mixed-signal processing circuits | Prasant Kumar Vallur, David Lin, Manoj N. Kulkarni, Priyadarshi Saxena | 2025-09-16 |
| 12386750 | Last level cache hierarchy in chiplet based processors | Krishnaiah Gummidipudi, Prasant Kumar Vallur, David Hugh McIntyre, Ramon Mangaser | 2025-08-12 |
| 12321294 | Data lane variation compensation for data rate enhancement | David Hugh McIntyre, Ramon Mangaser, Prasant Kumar Vallur, Manoj N. Kulkarni | 2025-06-03 |