Issued Patents 2024
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12170323 | Nano transistors with source/drain having side contacts to 2-D material | Chao-Ching Cheng, Yi-Tse Hung, Hung-Li Chiang, Lain-Jong Li, Jin Cai | 2024-12-17 |
| 12165729 | Semiconductor device including memory cells and method for manufacturing thereof | Hung-Li Chiang, Yu-Sheng Chen, Chao-Ching Cheng | 2024-12-10 |
| 12144268 | Semiconductor structure and method of manufacture | Kerem Akarvardar, Yu-Chao Lin, Wei-Sheng Yun, Shao-Ming Yu, Tung Ying Lee | 2024-11-12 |
| 12142533 | Method of manufacturing a semiconductor device and a semiconductor device | Chao-Ching Cheng, I-Sheng Chen, Hung-Li Chiang | 2024-11-12 |
| 12136672 | FeFET of 3D structure for capacitance matching | Hung-Li Chiang, Chih-Sheng Chang | 2024-11-05 |
| 12069970 | Memory device, method for configuring memory cell in N-bit memory unit, and memory array | Hung-Li Chiang, Jer-Fu Wang, Meng-Fan Chang | 2024-08-20 |
| 12062696 | Manufacturing method of semiconductor device | Yi-Tse Hung, Ang-Sheng Chou, Hung-Li Chiang, Chao-Ching Cheng | 2024-08-13 |
| 12046665 | Forming semiconductor structures with two-dimensional materials | Chao-Ching Cheng, Hung-Li Chiang, Chun-Chieh Lu, Ming-Yang Li | 2024-07-23 |
| 12040400 | Method for forming semiconductor device structure with nanostructure | Hung-Li Chiang, Yu-Chao Lin, Chao-Ching Cheng, Tung Ying Lee | 2024-07-16 |
| 12035532 | Memory array and memory device | Hung-Li Chiang, Jer-Fu Wang, Chao-Ching Cheng, Chih Chieh Yeh | 2024-07-09 |
| 12022752 | Methods of forming memory devices | Hung-Li Chiang, Jer-Fu Wang, Chao-Ching Cheng | 2024-06-25 |
| 11984476 | Isolation structures of semiconductor devices | Hung-Li Chiang, Chao-Ching Cheng, I-Sheng Chen | 2024-05-14 |
| 11967375 | Memory cell with built-in amplifying function, memory device and method using the same | Hung-Li Chiang, Chao-Ching Cheng, Yu-Sheng Chen, Hon-Sum Philip Wong | 2024-04-23 |
| 11963369 | Memory array with asymmetric bit-line architecture | Hung-Li Chiang, Chao-Ching Cheng, Jung-Piao Chiu, Yu-Sheng Chen | 2024-04-16 |
| 11955527 | Nano transistors with source/drain having side contacts to 2-D material | Chao-Ching Cheng, Yi-Tse Hung, Hung-Li Chiang, Lain-Jong Li, Jin Cai | 2024-04-09 |
| 11948941 | Semiconductor device, integrated circuit and methods of manufacturing the same | Yi-Tse Hung, Ang-Sheng Chou, Hung-Li Chiang, Chao-Ching Cheng | 2024-04-02 |
| 11929115 | Memory device with SRAM cells assisted by non-volatile memory cells and operation method thereof | Jer-Fu Wang, Hung-Li Chiang, Yi-Tse Hung, Meng-Fan Chang | 2024-03-12 |
| 11929425 | Nanowire stack GAA device with inner spacer | Tzu-Chung Wang, Chao-Ching Cheng, Tung Ying Lee | 2024-03-12 |
| 11923413 | Semiconductor structure with extended contact structure | Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang +3 more | 2024-03-05 |
| 11923252 | Semiconductor device and method for manufacturing the same | Sai-Hooi Yeong, Bo-Feng Young, Chi On Chui, Chih Chieh Yeh, Cheng-Hsien Wu +2 more | 2024-03-05 |
| 11910732 | Resistive memory devices using a carbon-based conductor line and methods for forming the same | Hung-Li Chiang, Chao-Ching Cheng, Lain-Jong Li | 2024-02-20 |
| 11903334 | Memory devices and methods of forming the same | Hung-Li Chiang, Jer-Fu Wang, Chao-Ching Cheng | 2024-02-13 |