Issued Patents 2024
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12176407 | Method of forming a transistor device with a gate structure having a pair of recess regions and a resistive protection layer within | Chen-Liang Chu, Chien-Chih Chou, Chih-Chang Cheng, Yi-Huan Chen, Kong-Beng Thei +2 more | 2024-12-24 |
| 12132108 | Dual gate structures for semiconductor devices | Po-Chih Su, Pei-Lun Wang, Jia-Rui Lee, Jyun-Guan Jhou | 2024-10-29 |
| 12074208 | Method of making triple well isolated diode | Chih-Chang Cheng, Fu-Yu Chu | 2024-08-27 |
| 12027526 | Breakdown voltage capability of high voltage device | Hsin-Chih Chiang, Tung-Yang Lin, Ming-Ta Lei | 2024-07-02 |
| 11967645 | Power MOSFETs structure | Yogendra Yadav, Chi-Chih Chen, Chih-Wen Yao | 2024-04-23 |
| 11923429 | Plate design to decrease noise in semiconductor devices | Chih-Chang Cheng, Fu-Yu Chu, Ming-Ta Lei, Shih-Fen Huang | 2024-03-05 |
| 11894459 | Dual gate structures for semiconductor devices | Po-Chih Su, Pei-Lun Wang, Jia-Rui Lee, Jyun-Guan Jhou | 2024-02-06 |