Issued Patents 2024
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12149255 | Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable | Raja Prabhu J, Ankit Seedher, Srinath Sridharan, Rakesh Gupta, Nitesh Naidu +2 more | 2024-11-19 |
| 11967965 | Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable | Raja Prabhu J, Ankit Seedher, Srinath Sridharan, Rakesh Gupta, Nitesh Naidu +2 more | 2024-04-23 |