Issued Patents 2024
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12149255 | Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable | Raja Prabhu J, Ankit Seedher, Srinath Sridharan, Nitesh Naidu, Shivam Agrawal +2 more | 2024-11-19 |
| 12026028 | Preventing reverse-current flow when an integrated circuit operates using power supplies of different magnitudes | Raja Prabhu J, Shuvadeep Mitra, Anurag Pulincherry, Ankit Seedher | 2024-07-02 |
| 11967965 | Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable | Raja Prabhu J, Ankit Seedher, Srinath Sridharan, Nitesh Naidu, Shivam Agrawal +2 more | 2024-04-23 |