Issued Patents 2024
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12149255 | Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable | Raja Prabhu J, Ankit Seedher, Srinath Sridharan, Rakesh Gupta, Nitesh Naidu +2 more | 2024-11-19 |
| 11967965 | Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable | Raja Prabhu J, Ankit Seedher, Srinath Sridharan, Rakesh Gupta, Nitesh Naidu +2 more | 2024-04-23 |
| 11923864 | Fast switching of output frequency of a phase locked loop (PLL) | Srinath Sridharan, Ankit Seedher, Raja Prabhu J, Purva Choudhary, Sandeep Sasi +1 more | 2024-03-05 |