Issued Patents 2024
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11996854 | Method and system for low noise sub-sampling phase lock loop (PLL) architecture with automatic dynamic frequency acquisition | Sushrant Monga | 2024-05-28 |
| 11909407 | Method and system of dynamically controlling reset signal of IQ divider | Praveen Rathee, Sanjeeb Kumar Ghosh, Avneesh Singh Verma | 2024-02-20 |