Issued Patents 2024
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11996854 | Method and system for low noise sub-sampling phase lock loop (PLL) architecture with automatic dynamic frequency acquisition | Vishnu Kalyanamahadevi Gopalan Jawarlal | 2024-05-28 |
| 11870614 | Method and system for high speed decision-feedback equalization (DFE) | — | 2024-01-09 |