Issued Patents 2024
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12174757 | Apparatus and methods for reducing latencies associated with link state transitions within die interconnect architectures | Prakhar Srivastava, Sridhar ANUMALA, Ramacharan Sundararaman, Sonali Jabreva, Khushboo KUMARI +1 more | 2024-12-24 |
| 12164448 | Mechanism to reduce exit latency for deeper power saving modes L2 in PCIe | Ravindranath DODDI, Prakhar Srivastava | 2024-12-10 |
| 12153527 | Data rate increase for faulty lane recovery in multiple lane data links | Prakhar Srivastava, Rajendra Varma Pusapati, Ravindranath DODDI, Yogananda Rao Chillariga | 2024-11-26 |
| 12079061 | Power management for peripheral component interconnect | Prakhar Srivastava, Ravindranath DODDI, Ravi Kumar SEPURI | 2024-09-03 |
| 12056364 | Write buffer and logical unit management in a data storage device | Yogananda Rao Chillariga, Prakhar Srivastava, Sonali Jabreva, Chintalapati BHARATH SAI VARMA | 2024-08-06 |
| 12019577 | Latency reduction for link speed switching in multiple lane data links | Prakhar Srivastava, Ravindranath DODDI, Ravi Kumar SEPURI | 2024-06-25 |
| 11934335 | Power management for peripheral component interconnect | Prakhar Srivastava, Ravindranath DODDI | 2024-03-19 |