Issued Patents 2024
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12164448 | Mechanism to reduce exit latency for deeper power saving modes L2 in PCIe | Santhosh Reddy AKAVARAM, Prakhar Srivastava | 2024-12-10 |
| 12153527 | Data rate increase for faulty lane recovery in multiple lane data links | Santhosh Reddy AKAVARAM, Prakhar Srivastava, Rajendra Varma Pusapati, Yogananda Rao Chillariga | 2024-11-26 |
| 12079061 | Power management for peripheral component interconnect | Prakhar Srivastava, Santhosh Reddy AKAVARAM, Ravi Kumar SEPURI | 2024-09-03 |
| 12019577 | Latency reduction for link speed switching in multiple lane data links | Prakhar Srivastava, Santhosh Reddy AKAVARAM, Ravi Kumar SEPURI | 2024-06-25 |
| 11934335 | Power management for peripheral component interconnect | Prakhar Srivastava, Santhosh Reddy AKAVARAM | 2024-03-19 |