Issued Patents 2024
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12183406 | Eliminating write disturb for system metadata in a memory sub-system | Zhenming Zhou, Zhenlei Shen, Charles See Yeung Kwong | 2024-12-31 |
| 12165709 | Memory cell voltage level selection | Murong Lang, Fangfang Zhu, Jiangli Zhu, Zhenming Zhou | 2024-12-10 |
| 12050808 | Selecting a write operation mode from multiple write operation modes | Zhenlei Shen, Fangfang Zhu, Jiangli Zhu | 2024-07-30 |
| 12045512 | Read refresh via signal calibration for non-volatile memories | Zhenming Zhou, Zhenlei Shen, Chih-Kuo Kao | 2024-07-23 |
| 12027211 | Partial block handling protocol in a non-volatile memory device | Zhongguang Xu, Murong Lang | 2024-07-02 |
| 11994945 | Managing write disturb for units of memory in a memory sub-system | Zhenming Zhou, Charles See Yeung Kwong | 2024-05-28 |
| 11989107 | Application of dynamic trim strategy in a die-protection memory sub-system | Charles See Yeung Kwong | 2024-05-21 |
| 11966591 | Apparatus with read level management and methods for operating the same | Murong Lang, Fangfang Zhu, Zhenming Zhou, Jiangli Zhu | 2024-04-23 |
| 11953973 | Prioritization of successful read recovery operations for a memory device | Naveen Bolisetty | 2024-04-09 |
| 11923001 | Managing the programming of an open translation unit | Murong Lang, Zhenming Zhou, Jian Huang, Jiangli Zhu, Nagendra Prasad Ganesh Rao +1 more | 2024-03-05 |
| 11914889 | Managing an adjustable write-to-read delay based on cycle counts in a memory sub-system | Murong Lang, Wei Wang, Frederick Adi, Zhenming Zhou, Jiangli Zhu | 2024-02-27 |
| 11894090 | Selective power-on scrub of memory units | Zhenlei Shen, Zhenming Zhou | 2024-02-06 |
| 11861178 | Managing a hybrid error recovery process in a memory sub-system | Zhongguang Xu, Jian Huang, Murong Lang, Zhenming Zhou | 2024-01-02 |