Issued Patents 2024
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12086410 | Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer | Amrita Mathuriya, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2024-09-10 |
| 12079475 | Ferroelectric memory chiplet in a multi-dimensional packaging | Amrita Mathuriya, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2024-09-03 |
| 12026034 | Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic | Amrita Mathuriya, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2024-07-02 |
| 12019492 | Method and apparatus for managing power in a multi-dimensional packaging | Amrita Mathuriya, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2024-06-25 |
| 12001266 | Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic | Amrita Mathuriya, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2024-06-04 |
| 11899613 | Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging | Amrita Mathuriya, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2024-02-13 |
| 11886884 | Branch prediction based on coherence operations in processors | Binh Pham, Patrick Lu, Jared W. Stark, IV | 2024-01-30 |
| 11875836 | Apparatus and method for endurance of non-volatile memory banks via wear leveling with linear indexing | Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2024-01-16 |
| 11869562 | Apparatus and method for endurance of non-volatile memory banks via wear leveling in a round robin fashion | Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2024-01-09 |