Issued Patents 2024
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12174783 | Systolic array of arbitrary physical and logical depth | Jorge Parra, Wei-Yu Chen, Kaiyu Chen, Varghese George, Junjie Gu +4 more | 2024-12-24 |
| 12093213 | Computing efficient cross channel operations in parallel computing machines using systolic arrays | Subramaniam Maiyuran, Jorge Parra, Chandra Gurram | 2024-09-17 |
| 12039001 | Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs | Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Shubra Marwaha, Chandra Gurram +3 more | 2024-07-16 |
| 12007935 | Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format | Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Jorge Parra, Chandra Gurram +3 more | 2024-06-11 |
| 11977885 | Utilizing structured sparsity in systolic arrays | Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Chandra Gurram, Chunhui Mei +10 more | 2024-05-07 |
| 11954063 | Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format | Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Jorge Parra, Chandra Gurram +3 more | 2024-04-09 |
| 11900502 | Compiler assisted register file write reduction | Chandra Gurram, Gang Chen, Subramaniam Maiyuran, Ashutosh Garg, Jorge Parra +3 more | 2024-02-13 |