Issued Patents 2024
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12174783 | Systolic array of arbitrary physical and logical depth | Jorge Parra, Wei-Yu Chen, Kaiyu Chen, Varghese George, Junjie Gu +4 more | 2024-12-24 |
| 12164884 | Tanh and sigmoid function execution | Shuai Mu, Cristina S. Anderson | 2024-12-10 |
| 12067394 | Native support for execution of get exponent, get mantisssa, and scale instructions within a graphics processing unit via reuse of fused multiply-add execution unit hardware logic | Shuai Mu, Cristina S. Anderson | 2024-08-20 |
| 12039001 | Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs | Jorge Parra, Supratim Pal, Ashutosh Garg, Shubra Marwaha, Chandra Gurram +3 more | 2024-07-16 |
| 12008067 | Sparse matrix multiplication acceleration mechanism | Mathew Nevin, Jorge Parra, Ashutosh Garg, Shubra Marwaha, Shubh Shah | 2024-06-11 |
| 12007935 | Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format | Shubra Marwaha, Ashutosh Garg, Supratim Pal, Jorge Parra, Chandra Gurram +3 more | 2024-06-11 |
| 11954063 | Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format | Shubra Marwaha, Ashutosh Garg, Supratim Pal, Jorge Parra, Chandra Gurram +3 more | 2024-04-09 |
| 11934797 | Mechanism to perform single precision floating point extended math operations | Abhishek Rhisheekesan, Shashank Lakshminarayana | 2024-03-19 |
| 11900114 | Systems and methods to skip inconsequential matrix operations | Elmoustapha Ould-Ahmed-Vall, William C. Rash, Varghese George, Rajesh M. Sankaran | 2024-02-13 |
| 11900502 | Compiler assisted register file write reduction | Chandra Gurram, Gang Chen, Supratim Pal, Ashutosh Garg, Jorge Parra +3 more | 2024-02-13 |