Issued Patents 2024
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12181966 | Reduction of latency impact of on-die error checking and correction (ECC) | Narasimha Lanka | 2024-12-31 |
| 12164373 | Memory chip with per row activation count having error correction code protection | Bill Nale, Lawrence D. BLANKENBECKLER, Ronald ANDERSON, Jongwon Lee | 2024-12-10 |
| 12087352 | Techniques to couple high bandwidth memory device on silicon substrate and package substrate | Chong J. Zhao, James A. McCall, Shigeki Tomishima, George Vergis | 2024-09-10 |
| 11989106 | Inline buffer for in-memory post package repair (PPR) | Jongwon Lee | 2024-05-21 |
| 11966286 | Read retry to selectively disable on-die ECC | Rajat Agarwal, Jongwon Lee | 2024-04-23 |
| 11954360 | Technology to provide accurate training and per-bit deskew capability for high bandwidth memory input/output links | Narasimha Lanka, Lohit Yerva | 2024-04-09 |