VC

Vivek Chickermane

CS Cadence Design Systems: 2 patents #13 of 141Top 10%
📍 Slaterville Springs, NY: #1 of 1 inventorsTop 100%
🗺 New York: #2,004 of 12,119 inventorsTop 20%
Overall (2024): #106,542 of 561,600Top 20%
2
Patents 2024

Issued Patents 2024

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
12055586 3D stacked die testing structure Sagar Kumar, Rajesh Khurana 2024-08-06
11947887 Test-point flop sharing with improved testability in a circuit design Krishna Vijaya Chakravadhanula, Brian Foutz, Prateek Kumar Rai, Sarthak Singhal, Christos Papameletis 2024-04-02