TK

Tharun Kumar Ksheerasagar

AM AMD: 1 patents #388 of 1,033Top 40%
📍 Chilpur, IN: #44 of 148 inventorsTop 30%
Overall (2024): #243,960 of 561,600Top 45%
1
Patents 2024

Issued Patents 2024

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
12086521 Circuit design simulation and clock event reduction Rohit Bhadana, Hemant Kashyap, Pratyush Ranjan 2024-09-10