Issued Patents 2024
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12165252 | Multi-accelerator compute dispatch | Maxim V. Kazakov, Prerit Dak | 2024-12-10 |
| 12067640 | Dynamically reconfigurable register file | Pramod Vasant Argade, Martin G. Sarov | 2024-08-20 |
| 11995351 | DMA engines configured to perform first portion data transfer commands with a first DMA engine and second portion data transfer commands with second DMA engine | Joseph L. Greathouse, Sean Keely, Alan Dodson Smith, Anthony Asaro, Ling Wang +2 more | 2024-05-28 |
| 11960399 | Relaxed invalidation for cache coherence | Akhil Arunkumar, Tarun Nakra, Maxim V. Kazakov | 2024-04-16 |