Issued Patents 2023
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11736594 | Low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware | Dhaval Shah, Sunil PURANIK, Manoj Karunakaran Nambiar, Ishtiyaque Shaikh, Piyush Manavar +1 more | 2023-08-22 |
| 11714742 | Synthesizing printf and scanf statements for generating debug messages in high-level synthesis (HLS) code | Sunil PURANIK, Manoj Karunakara Nambiar, Swapnil RODI | 2023-08-01 |
| 11611638 | Re-assembly middleware in FPGA for processing TCP segments into application layer messages | Dhaval Shah, Sunil PURANIK, Manoj Karunakaran Nambiar, Ishtiyaque Shaikh | 2023-03-21 |