Issued Patents 2023
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11769539 | Integrated circuit with asymmetric arrangements of memory arrays | He-Zhou WAN, Kuan-Lun Cheng, Ching-Wei Wu | 2023-09-26 |
| 11735251 | Timing control circuit of memory device with tracking word line and tracking bit line | Lu-Ping KONG, Kuan-Lun Cheng, He-Zhou WAN | 2023-08-22 |
| 11721374 | Control circuit of memory device | He-Zhou WAN, Pei-Le LI, Ching-Wei Wu | 2023-08-08 |
| 11705174 | Integrated circuit with asymmetric arrangements of memory arrays | He-Zhou WAN, Kuan-Lun Cheng, Ching-Wei Wu | 2023-07-18 |
| 11651134 | Method of certifying safety levels of semiconductor memories in integrated circuits | Ching-Wei Wu, Ming-En Bu, He-Zhou WAN, Hidehiro Fujiwara | 2023-05-16 |
| 11557336 | Static random access memory with adaptive precharge signal generated in response to tracking operation | He-Zhou WAN, Lu-Ping KONG, Wei-Yang Jiang | 2023-01-17 |
| 11545191 | Circuit and method of operating the same | Ching-Wei Wu, He-Zhou WAN, Ming-En Bu | 2023-01-03 |