Issued Patents 2023
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11856781 | Three-dimensional memory device and method | TsuChing Yang, Hung-Chang Sun, Kuo-Chang Chiang, Yu-Wei Jiang | 2023-12-26 |
| 11856779 | Semiconductor device, memory array and method of forming the same | Chung-Te Lin | 2023-12-26 |
| 11856775 | Flash memory structure and method of forming the same | Chung-Te Lin, Yung-Yu Chen | 2023-12-26 |
| 11832450 | Embedded ferroelectric FinFET memory device | Bo-Feng Young, Chung-Te Lin, Sai-Hooi Yeong, Yu-Ming Lin, Chih-Yu Chang +1 more | 2023-11-28 |
| 11818882 | Vertical fuse memory in one-time program memory cells | Chung-Te Lin | 2023-11-14 |
| 11805658 | Magnetic random access memory and manufacturing method thereof | Hui-Hsien Wei, Chung-Te Lin, Han-Ting Tsai, Tai-Yen Peng, Yu-Teng Dai +2 more | 2023-10-31 |
| 11800703 | Vertical fuse memory in one-time program memory cells | Chung-Te Lin | 2023-10-24 |
| 11800718 | Semiconductor memory device with gate line passing through source/drain, channel and dielectric layers over via | Chung-Te Lin | 2023-10-24 |
| 11792999 | Bipolar selector with independently tunable threshold voltages | Chung-Te Lin, Min Cao, Randy B. Osborne | 2023-10-17 |
| 11785779 | Method for forming a semiconductor memory structure using a liner layer as an etch stop | Yu-Wei Jiang, Feng-Cheng Yang, Chung-Te Lin | 2023-10-10 |
| 11770935 | 3D ferroelectric memory | Chung-Te Lin | 2023-09-26 |
| 11729987 | Memory array source/drain electrode structures | Kuo-Chang Chiang, Hung-Chang Sun, TsuChing Yang, Yu-Wei Jiang | 2023-08-15 |
| 11729983 | Peripheral circuitry under array memory device and method of fabricating thereof | Chung-Te Lin | 2023-08-15 |
| 11729988 | Memory device comprising conductive pillars and method of forming the same | Yu-Wei Jiang, TsuChing Yang, Hung-Chang Sun, Kuo-Chang Chiang | 2023-08-15 |
| 11723210 | High selectivity isolation structure for improving effectiveness of 3D memory fabrication | Tsu Ching Yang, Feng-Cheng Yang, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun +2 more | 2023-08-08 |
| 11723199 | Protective liner layers in 3D memory structure | Tsu Ching Yang, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, Chen-Jun Wu +2 more | 2023-08-08 |
| 11721767 | Oxide semiconductor transistor structure in 3-D device and methods of forming the same | Kuo-Chang Chiang, Hung-Chang Sun, TsuChing Yang, Yu-Wei Jiang, Feng-Cheng Yang +1 more | 2023-08-08 |
| 11721747 | Integrated circuit, transistor and method of fabricating the same | Yu-Wei Jiang, Feng-Cheng Yang, Chung-Te Lin | 2023-08-08 |
| 11710790 | Memory array channel regions | Kuo-Chang Chiang, Hung-Chang Sun, TsuChing Yang, Yu-Wei Jiang | 2023-07-25 |
| 11696448 | Memory device and method of forming the same | Hung-Chang Sun, TsuChing Yang, Yu-Wei Jiang, Kuo-Chang Chiang | 2023-07-04 |
| 11683988 | Semiconductor device | Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee +2 more | 2023-06-20 |
| 11672123 | Three-dimensional memory array with local line selector | Chen-Jun Wu, Yu-Wei Jiang | 2023-06-06 |
| 11640974 | Memory array isolation structures | Kuo-Chang Chiang, Hung-Chang Sun, TsuChing Yang, Yu-Wei Jiang | 2023-05-02 |
| 11569165 | Memory cell array, semiconductor device including the same, and manufacturing method thereof | TsuChing Yang, Hung-Chang Sun, Yu-Wei Jiang, Kuo-Chang Chiang | 2023-01-31 |
| 11545201 | Memory device with unipolar selector | — | 2023-01-03 |