Issued Patents 2023
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11854965 | Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability | Yu-Teng Dai, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao | 2023-12-26 |
| 11842924 | Dual etch-stop layer structure | Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Chih Wei Lu, Chung-Ju Lee | 2023-12-12 |
| 11842966 | Integrated chip with inter-wire cavities | Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai +2 more | 2023-12-12 |
| 11798840 | Self-assembled dielectric on metal RIE lines to increase reliability | Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Yu-Teng Dai, Chung-Ju Lee | 2023-10-24 |
| 11798910 | Self-aligned interconnect structure | Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai, Wei-Hao Liao | 2023-10-24 |
| 11756884 | Interconnection structure and methods of forming the same | Wei-Hao Liao, Hsi-Wen Tien, Yu-Teng Dai, Chih Wei Lu, Chung-Ju Lee | 2023-09-12 |
| 11688782 | Semiconductor structure and method for forming the same | Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Yu-Teng Dai, Chung-Ju Lee | 2023-06-27 |
| 11676862 | Semiconductor device structure and methods of forming the same | Hwei-Jay CHU, Chieh-Han Wu, Cheng-Hsiung Tsai, Chung-Ju Lee | 2023-06-13 |
| 11652054 | Dielectric on wire structure to increase processing window for overlying via | Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai, Wei-Hao Liao | 2023-05-16 |
| 11569127 | Double patterning approach by direct metal etch | Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Chih Wei Lu, Chung-Ju Lee | 2023-01-31 |