Issued Patents 2023
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11847468 | Data defragmentation for a system boot procedure having random indexes indicating a relationship between sequential logical addresses and random logical addresses | Francesco Basso, Luca Porzio, Roberto Izzi, Francesco Falanga, Nadav Grosz | 2023-12-19 |
| 11789661 | Virtual partition management | Angelo Della Monica, Eric Kwok Fung Yuen, Pasquale Cimmino, Francesco Falanga | 2023-10-17 |
| 11720489 | Scheme to improve efficiency of device garbage collection in memory devices | Xinghui Duan, Giuseppe D'Eliseo, Lalla Fatima Drissi, Giuseppe Ferrari, Eric Kwok Fung Yuen | 2023-08-08 |
| 11705201 | Log data storage for flash memory | Paolo Papa, Luigi Esposito, Eric Kwok Fung Yuen, Gerard J. Perdaems | 2023-07-18 |
| 11698826 | Fatal error logging in a memory device | Luigi Esposito, Paolo Papa, Erika Morvillo | 2023-07-11 |
| 11675709 | Reading sequential data from memory using a pivot table | Giuseppe D'Eliseo, Carminantonio Manganelli, Paolo Papa, Yoav Weinberg, Giuseppe Ferrari +1 more | 2023-06-13 |
| 11663120 | Controlling NAND operation latency | Giuseppe D'Eliseo, Luigi Esposito, Xinghui Duan, Lucia Santojanni | 2023-05-30 |
| 11662935 | Adaptive data relocation for improved data management for memory | Luigi Esposito, Alberto Sassara, Paolo Papa | 2023-05-30 |
| 11650931 | Hybrid logical to physical caching scheme of L2P cache and L2P changelog | Carminantonio Manganelli, Yoav Weinberg, Alberto Sassara, Paolo Papa, Luigi Esposito +2 more | 2023-05-16 |
| 11635894 | Clustered parity for NAND data placement schema | Paolo Papa, Carminantonio Manganelli, Giuseppe D'Eliseo, Alberto Sassara | 2023-04-25 |
| 11586547 | Instruction caching scheme for memory devices | Crescenzo Attanasio, Pasquale Cimmino, Nicola Cavaliere, Francesco Falanga | 2023-02-21 |