Issued Patents 2023
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11837296 | Non-volatile memory with adjusted bit line voltage during verify | Jiahui Yuan, Ohwon Kwon | 2023-12-05 |
| 11790992 | State dependent VPVD voltages for more uniform threshold voltage distributions in a memory device | Huai-Yuan Tseng | 2023-10-17 |
| 11758718 | Three dimensional memory device containing truncated channels and method of operating the same with different erase voltages for different bit lines | Abhijith Prakash, Keyur Payak, Jiahui Yuan, Huai-Yuan Tseng, Shinsuke Yada +1 more | 2023-09-12 |
| 11699494 | Peak and average ICC reduction by tier-based sensing during program verify operations of non-volatile memory structures | Xue Bai Pitner, Deepanshu Dutta, Huai-Yuan Tseng, Ravi Kumar | 2023-07-11 |
| 11664075 | Sub-block programming mode with multi-tier block | Jiahui Yuan, Tomer Eliash | 2023-05-30 |
| 11600343 | Efficient read of NAND with read disturb mitigation | Tomer Eliash, Huai-Yuan Tseng | 2023-03-07 |
| 11587619 | Block configuration for memory device with separate sub-blocks | Jiahui Yuan, Deepanshu Dutta | 2023-02-21 |