Issued Patents 2023
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11709793 | Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format | Shubra Marwaha, Ashutosh Garg, Supratim Pal, Jorge Parra, Chandra Gurram +3 more | 2023-07-25 |
| 11669329 | Instructions and logic for vector multiply add with zero skipping | Supratim Pal, Sasikanth Avancha, Ishwar Bhati, Wei-Yu Chen, Dipankar Das +7 more | 2023-06-06 |
| 11640297 | Instruction and logic for systolic dot product with accumulate | Guei-Yuan Lueh, Supratim Pal, Ashutosh Garg, Chandra Gurram, Jorge Parra +10 more | 2023-05-02 |
| 11636174 | Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs | Jorge Parra, Supratim Pal, Ashutosh Garg, Shubra Marwaha, Chandra Gurram +3 more | 2023-04-25 |
| 11625244 | Native support for execution of get exponent, get mantissa, and scale instructions within a graphics processing unit via reuse of fused multiply-add execution unit hardware logic | Shuai Mu, Cristina S. Anderson | 2023-04-11 |
| 11593069 | Use of a single instruction set architecture (ISA) instruction for vector normalization | Abhishek Rhisheekesan, Supratim Pal, Shashank Lakshminarayana | 2023-02-28 |
| 11579878 | Register sharing mechanism to equally allocate disabled thread registers to active threads | Pratik J. Ashar, Supratim Pal, Wei-Yu Chen, Guei-Yuan Lueh | 2023-02-14 |