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Method to limit the time a semiconductor device operates above a maximum operating voltage |
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| 11782836 |
Multiprocessor system cache management with non-authority designation |
Jason D. Kohl, Winston Herring, Tu-An T. Nguyen, Gregory W. Alexander, Timothy C. Bronson |
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| 11775445 |
Translation support for a virtual cache |
Markus Helms, Ulrich Mayer, Martin Recktenwald, Johannes C. Reichart, Anthony Saporito +1 more |
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| 11762659 |
Handling an input/output store instruction |
Christoph Raisch, Marco Kraemer, Frank Lehnert, Matthias Klein, Jonathan D. Bradbury +2 more |
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| 11675513 |
Selectively shearing data when manipulating data during record processing |
Scott B. Compton, Jeffrey R. Suarez, Matthew Michael Garcia Pardini, Dominik Steenken, Sri Hari Kolusu +1 more |
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| 11646861 |
Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes |
Patrick J. Meaney, Ashutosh Mishra, Paul Allen Ganfield, Logan I. Friedman, Jentje Leenstra +3 more |
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| 11620231 |
Lateral persistence directory states |
Ram Sai Manoj Bamdhamravuri, Craig R. Walters, Timothy C. Bronson, Gregory W. Alexander, Hieu T. Huynh +4 more |
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| 11593107 |
Handling an input/output store instruction |
Christoph Raisch, Marco Kraemer, Frank Lehnert, Matthias Klein, Jonathan D. Bradbury +2 more |
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| 11586542 |
Reducing cache transfer overhead in a system |
Christian Zoellin, Chung-Lung K. Shum, Martin Recktenwald, Anthony Saporito, Aaron Tsai |
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| 11579874 |
Handling an input/output store instruction |
Christoph Raisch, Marco Kraemer, Frank Lehnert, Matthias Klein, Jonathan D. Bradbury +2 more |
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