KP

Kailash Pralhad Pawar

SY Synopsys: 2 patents #11 of 289Top 4%
📍 Pune, CA: #14 of 44 inventorsTop 35%
Overall (2023): #138,014 of 537,848Top 30%
2
Patents 2023

Issued Patents 2023

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
11797739 Endpoint path margin based integrated circuit design using sub-critical timing paths Deyuan Guo 2023-10-24
11681842 Latency offset in pre-clock tree synthesis modeling Paul Eugene Richard Lippens, Darren Charles Cronquist 2023-06-20