| 11847463 |
Masked multi-lane instruction memory fault handling using fast and slow execution paths |
Kai Troester, Scott Thomas Bingham, John M. King, Michael Estlick, Robert Weidner |
2023-12-19 |
| 11709681 |
Differential pipeline delays in a coprocessor |
Jay Fleischman, Michael Estlick, Michael Sedmak, Sneha V. Desai |
2023-07-25 |
| 11573801 |
Method and apparatus for executing vector instructions with merging behavior |
Eric Dixon, Theodore Carlson, Ruchir Dalal, Michael Estlick |
2023-02-07 |
| 11567554 |
Clock mesh-based power conservation in a coprocessor based on in-flight instruction characteristics |
Jay Fleischman, Michael Estlick, Michael Sedmak, Sneha V. Desai |
2023-01-31 |
| 11544065 |
Bit width reconfiguration using a shadow-latch configured register file |
Arun A. Nair, Todd Baumgartner, Michael Estlick |
2023-01-03 |