Issued Patents 2022
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11476157 | Method of manufacturing a metal-oxide-semiconductor field-effect transistor (MOSFET) having low off-state capacitance due to reduction of off-state capacitance of back-end-of-line (BEOL) features of the MOSFET | Tsung-Han Tsai, Shih-Lu HSU, Kun-Tsang Chuang | 2022-10-18 |
| 11462642 | Source/drain epitaxial layer profile | Hsin-Chi Chen, Kun-Tsang Chuang | 2022-10-04 |
| 11462550 | SRAM structure | Shun-Chi TSAI, Chih-Ming Lee, Chi-Yen Lin, Kuo-Hung Lo | 2022-10-04 |
| 11417749 | Semiconductor arrangement with airgap and method of forming | Wang Po-Jen, Kun-Tsang Chuang, Tsung-Han Tsai | 2022-08-16 |
| 11404537 | Semiconductor device with air-void in spacer | Kun-Tsang Chuang, Hsin-Chi Chen | 2022-08-02 |
| 11398403 | Multiple thickness semiconductor-on-insulator field effect transistors and methods of forming the same | Po-Jen Wang, Kun-Tsang Chuang | 2022-07-26 |
| 11367778 | MOSFET device structure with air-gaps in spacer and methods for forming the same | Po-Jen Wang, Kun-Tsang Chuang | 2022-06-21 |
| 11348944 | Semiconductor wafer with devices having different top layer thicknesses | Kuan-Liang Liu, Wang Po-Jen, Kun-Tsang Chuang, Hsin-Chi Chen | 2022-05-31 |
| 11335638 | Reducing RC delay in semiconductor devices | Kun-Tsang Chuang, Po-Jen Wang | 2022-05-17 |
| 11309268 | Method of designing a layout, method of making a semiconductor structure and semiconductor structure | Chih-Ming Lee, Chi-Yen Lin, Wen-Chang Kuo, C. C. Liu | 2022-04-19 |
| 11264456 | Isolation regions for reduced junction leakage | Hsin-Chi Chen, Kun-Tsang Chuang | 2022-03-01 |
| 11257902 | SOI device structure for robust isolation | Lin-Chen Lu, Tsung-Han Tsai, Po-Jen Wang | 2022-02-22 |