SS

Stanley Seungchul Song

QU Qualcomm: 10 patents #188 of 2,071Top 10%
📍 San Diego, CA: #164 of 4,447 inventorsTop 4%
🗺 California: #1,198 of 65,961 inventorsTop 2%
Overall (2022): #7,705 of 548,613Top 2%
10
Patents 2022

Issued Patents 2022

Showing 1–10 of 10 patents

Patent #TitleCo-InventorsDate
11515289 Stacked die integrated with package voltage regulators Bharani Chava, Abinash ROY, Jonghae Kim 2022-11-29
11502079 Integrated device comprising a CMOS structure comprising well-less transistors Hyunwoo Park, Peijie Feng 2022-11-15
11444068 Three-dimensional (3D) integrated circuit device having a backside power delivery network Jonghae Kim, Periannan Chidambaram, Pratyush Kamal 2022-09-13
11437379 Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits Deepak Sharma, Bharani Chava, Hyeokjin Lim, Peijie Feng, Seung H. Kang +6 more 2022-09-06
11404374 Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods Hyeokjin Lim, Foua Vang, Seung H. Kang 2022-08-02
11310911 Three-dimensional (3D) integrated circuit (IC) integration of an embedded chip and a preformed metal routing structure Jonghae Kim, Periannan Chidambaram 2022-04-19
11302638 Hybrid conductor integration in power rail John Jianhong Zhu, Kern Rim 2022-04-12
11270991 Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS) BEOL (BS-BEOL) power routing for current flow organization, and related methods Bharani Chava, Mohammed Yousuff Shariff 2022-03-08
11257917 Gate-all-around (GAA) transistors with additional bottom channel for reduced parasitic capacitance and methods of fabrication Jun Yuan, Peijie Feng, Kern Rim 2022-02-22
11244895 Intertwined well connection and decoupling capacitor layout structure for integrated circuits Ramesh MANCHANA, Sudheer Chowdary Gali, Biswa Ranjan PANDA, Dhaval Sejpal 2022-02-08