| 11501150 |
Neural network architecture |
Mbou Eyole, Fernando Garcia Redondo |
2022-11-15 |
| 11494256 |
Memory scanning operation in response to common mode fault signal |
Milosch Meriac, Emre Ozer, Xabier Iturbe, Balaji Venu |
2022-11-08 |
| 11468305 |
Hybrid memory artificial neural network hardware accelerator |
Urmish Ajit Thakker, Ganesh Suryanarayan Dasika |
2022-10-11 |
| 11444625 |
Clock phase-shifting techniques in physical layout design |
Benoit Labbe, Thanusree Achuthan |
2022-09-13 |
| 11423985 |
Devices and methods for controlling write operations |
Fernando Garcia Redondo, Glen Arnold Rosendale, George McNeil Lattimore, Mudit Bhargava |
2022-08-23 |
| 11366779 |
System-in-package architecture with wireless bus interconnect |
Benjamin James Fletcher, James Edward Myers, Terrence Sui Tung Mak |
2022-06-21 |
| 11355192 |
CES-based latching circuits |
Robert Campbell Aitken, Vikas Chandra, Bal S. Sandhu, George McNeil Lattimore, John Philip Biggs +2 more |
2022-06-07 |
| 11334788 |
Neural network including memory elements implemented at nodes |
Rune Holm |
2022-05-17 |
| 11232236 |
Dynamic response of power delivery network for attestation and identification |
Hugo John Martin Vincent, Milosch Meriac, Vasileios Tenentes |
2022-01-25 |