| 11537306 |
Cold data detector in memory system |
Daigo Toyama |
2022-12-27 |
| 11538516 |
Column selector architecture with edge mat optimization |
Hiroshi Akamatsu |
2022-12-27 |
| 11514977 |
Memory devices implementing data-access schemes for digit lines proximate to edges of column planes, and related devices, systems, and methods |
Jongtae Kwak |
2022-11-29 |
| 11502089 |
Three-dimensional fuse architectures and related systems, methods, and apparatuses |
Daigo Toyama |
2022-11-15 |
| 11501815 |
Sensing scheme for a memory with shared sense components |
Tae H. Kim, Scott J. Derner |
2022-11-15 |
| 11495283 |
Integrated assembly with memory array over base, sense amplifiers in base, and vertically-extending digit lines associated with the memory array |
Beau D. Barry |
2022-11-08 |
| 11472915 |
Porous compositions and related methods |
Timothy M. Swager, Zachary Smith, Sharon Sheau-Pyng Lin, Francesco Maria Benedetti |
2022-10-18 |
| 11443788 |
Reference-voltage-generators within integrated assemblies |
Takamasa Suzuki, Yasuo Satoh, Hyunui Lee |
2022-09-13 |
| 11443780 |
Vertical access line multiplexor |
Beau D. Barry, Tae H. Kim, Christopher John Kawamura |
2022-09-13 |
| 11423973 |
Contemporaneous sense amplifier timings for operations at internal and edge memory array mats |
— |
2022-08-23 |
| 11423972 |
Integrated assemblies |
Jiyun Li |
2022-08-23 |
| 11398266 |
Integrated assemblies having memory cells with capacitive units and reference-voltage-generators with resistive units |
Hyunui Lee, Takamasa Suzuki, Yasuo Satoh |
2022-07-26 |
| 11386948 |
Multiplexors under an array of memory cells |
Tae H. Kim |
2022-07-12 |
| 11380387 |
Multiplexor for a semiconductor device |
Tae H. Kim |
2022-07-05 |
| 11380376 |
Apparatuses and methods to perform low latency access of a memory |
Daigo Toyama |
2022-07-05 |
| 11367476 |
Bit line equalization driver circuits and related apparatuses, methods, and computing systems to avoid degradation of pull-down transistors |
Sang-Kyun Park |
2022-06-21 |
| 11361814 |
Column selector architecture with edge mat optimization |
Hiroshi Akamatsu |
2022-06-14 |
| 11302377 |
Apparatuses and methods for dynamic targeted refresh steals |
Liang Li, Yu Zhang |
2022-04-12 |
| 11290103 |
Charge transfer between gate terminals of subthreshold current reduction circuit transistors and related apparatuses and methods |
Hiroshi Akamatsu, Toru Ishikawa |
2022-03-29 |
| 11282569 |
Apparatus with latch balancing mechanism and methods for operating the same |
Hiroshi Akamatsu |
2022-03-22 |
| 11250903 |
Apparatus for supplying power supply voltage to semiconductor chip including volatile memory cell |
Chikara Kondo, Daigo Toyama |
2022-02-15 |
| 11237579 |
Apparatuses and methods for ZQ calibration |
Yasuo Satoh |
2022-02-01 |
| 11237734 |
High throughput DRAM with distributed column access |
— |
2022-02-01 |
| 11217297 |
Techniques for reducing row hammer refresh |
Yutaka Ito |
2022-01-04 |
