Issued Patents 2022
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11521686 | Memory apparatus and method of operation using state bit-scan dependent ramp rate for peak current reduction during program operation | Hua-Ling Cynthia Hsu, Huai-Yuan Tseng, Fanglin Zhang | 2022-12-06 |
| 11508450 | Dual time domain control for dynamic staggering | Huai-Yuan Tseng, Deepanshu Dutta | 2022-11-22 |
| 11475959 | Reduced program time for memory cells using negative bit line voltage for enhanced step up of program bias | Sujjatul Islam, Xue Bai Pitner | 2022-10-18 |
| 11475958 | Negative bit line biasing during quick pass write programming | Huai-Yuan Tseng, Swaroop Kaza, Tomer Eliash | 2022-10-18 |
| 11456333 | Three-dimensional NAND memory device containing two terminal selector and methods of using and making thereof | Jiahui Yuan, Deepanshu Dutta, Christopher J. Petti | 2022-09-27 |
| 11417400 | Controlling timing and ramp rate of program-inhibit voltage signal during programming to optimize peak current | Huai-Yuan Tseng, Deepanshu Dutta | 2022-08-16 |
| 11398280 | Lockout mode for reverse order read operation | Deepanshu Dutta, Huai-Yuan Tseng, Ravi Kumar | 2022-07-26 |
| 11386968 | Memory apparatus and method of operation using plane dependent ramp rate and timing control for program operation | Huai-Yuan Tseng, Tomer Eliash | 2022-07-12 |
| 11385810 | Dynamic staggering for programming in nonvolatile memory | Deepanshu Dutta, Huai-Yuan Tseng | 2022-07-12 |
| 11373710 | Time division peak power management for non-volatile storage | Hua-Ling Cynthia Hsu, Mark Murin, Mark Shlick | 2022-06-28 |
| 11361835 | Countermeasure for reducing peak current during programming by optimizing timing of latch scan operations | Fanglin Zhang, Huai-Yuan Tseng | 2022-06-14 |
| 11355208 | Triggering next state verify in progam loop for nonvolatile memory | Fanglin Zhang, Zhuojie Li, Huai-Yuan Tseng | 2022-06-07 |
| 11335413 | Ramp rate control for peak and average current reduction of open blocks | Huai-Yuan Tseng, Deepanshu Dutta | 2022-05-17 |
| 11335411 | Erase operation for memory device with staircase word line voltage during erase pulse | Keyur Payak, Huai-Yuan Tseng | 2022-05-17 |
| 11328754 | Pre-charge timing control for peak current based on data latch count | Juan Lee, Huai-Yuan Tseng | 2022-05-10 |
| 11315648 | Dynamic tier selection for program verify in nonvolatile memory | Dengtao Zhao, Huai-Yuan Tseng | 2022-04-26 |
| 11270776 | Countermeasure for reducing peak current during program operation under first read condition | Huai-Yuan Tseng, Deepanshu Dutta | 2022-03-08 |
| 11250892 | Pre-charge ramp rate control for peak current based on data latch count | Juan Lee, Huai-Yuan Tseng | 2022-02-15 |
| 11226772 | Peak power reduction management in non-volatile storage by delaying start times operations | Mark Murin, Hua-Ling Cynthia Hsu, Tomer Eliash, Huai-Yuan Tseng, Deepanshu Dutta | 2022-01-18 |