Issued Patents 2022
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11487506 | Condition code anticipator for hexadecimal floating point | Petra Leber, Kerstin Claudia Schelm, Cedric Lichtenau | 2022-11-01 |
| 11455142 | Ultra-low precision floating-point fused multiply-accumulate unit | Ankur Agrawal, Kailash Gopalakrishnan, Bruce M. Fleischer, Balaram Sinharoy, Mingu Kang | 2022-09-27 |
| 11360769 | Decimal scale and convert and split to hexadecimal floating point instruction | Eric M. Schwarz, Petra Leber, Kerstin Claudia Schelm, Reid T. Copeland, Xin Guo +1 more | 2022-06-14 |
| 11347517 | Reduced precision based programmable and SIMD dataflow architecture | Kailash Gopalakrishnan, Sunil K. Shukla, Jungwook Choi, Bruce M. Fleischer, Vijayalakshmi Srinivasan +2 more | 2022-05-31 |
| 11314482 | Low latency floating-point division operations | Thomas W. Fox, Bruce M. Fleischer | 2022-04-26 |
| 11275561 | Mixed precision floating-point multiply-add operation | Andreas Wagner, Brian W. Thompto | 2022-03-15 |
| 11221826 | Parallel rounding for conversion from binary floating point to binary coded decimal | Stefan Payer, Razvan Peter Figuli, Revital Arieli | 2022-01-11 |
| 11216281 | Facilitating data processing using SIMD reduction operations across SIMD lanes | Bruce M. Fleischer, Kailash Gopalakrishnan, Jinwook Oh, Sunil K. Shukla | 2022-01-04 |